The invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a variable even-number clock divider circuit having duty cycle correction and optional phase shift.
Digital circuits such as board level systems and integrated circuit (IC) devices, including programmable logic devices (PLDS) and microprocessors, use clocking signals for a variety of reasons. For example, synchronous systems use global clock signals to synchronize various circuits across the board or IC device.
However, as the complexity of digital circuits increases, clocking schemes for synchronous systems become more complicated. Many complex digital circuits such as PLDs and microprocessors have multiple clock signals at different frequencies. For example, in some microprocessors, internal circuits are clocked by a first clock signal at a first frequency while input/output (I/O) circuits are clocked by a second clock signal at a second frequency. Typically, the second frequency is slower than the first frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals. However, clock generating circuits typically consume a large amount of device or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from an input clock signal.
FIG. 1A shows a conventional clock divider 100 that receives an input clock signal ICLK and generates a divided-by-two clock signal CLKD2, a divided-by-four clock signal CLKD4, a divided-by-eight clock signal CLKD8, and a divided-by-sixteen clock signal CLKD16. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Clock divider 100 comprises a 4-bit counter 100. Input clock signal ICLK is applied to the clock terminal of 4-bit counter 110. 4-Bit counter 110 drives clock signals CLKD2, CLKD4, CLKD8, and CLKD16 on output terminals O0, O1, O2, and O3, respectively. Output terminals O0 through O3 provide the least significant bit through the most significant bit of 4-bit counter 100, respectively.
FIG. 1B is a timing diagram for clock divider 100. As can easily be seen from FIG. 1B, if input clock signal ICLK has a clock period P, then divide-by-two clock signal CLKD2 has a clock period of 2P. Similarly, divide-by-four clock signal CLKD4 has a period of 4P, and so forth. Thus, the frequency of clock signal CLKD2 is half the frequency of input clock signal ICLK, the frequency of clock signal CLKD4 is one-fourth the frequency of signal ICLK, and so forth.
Including a clock divider in an IC device typically carries a timing penalty, whether or not the clock divider is in use. FIG. 2A shows a first clock driver circuit in an IC where a clock divider is not included. The clock driver circuit 200 includes a driver 201 that accepts an input clock signal from clock pad 202, and applies the signal to clock tree 203. FIG. 2B shows a second clock driver circuit 210, which includes an optional clock divider 204. The designer can either include clock divider 204 in the circuit, or bypass the clock divider, under the control of multiplexer 205.
FIG. 2B clearly shows that whether or not the clock divider is included in the clock path, there is an additional delay D210 in the circuit of FIG. 2B compared to that of FIG. 2A. If the clock divider is bypassed, there is added delay in the bypass line and a propagation delay through the multiplexer 205. If the clock divider is included in the circuit, there are the added propagation delays of both the multiplexer and the clock divider. In either case, the total delay through the clock driver circuit is increased.
If a clock divider such as that shown in FIG. 1 is placed into the clock driver circuit of FIG. 2B, the result is a clock tree driven by a flip-flop (from 4-bit counter 110 of FIG. 1) through a multiplexer (e.g., multiplexer 205 of FIG. 2B). Clearly, neither a flip-flop nor an unbuffered multiplexer have the drive capability to drive a large clock treexe2x80x94the resulting clock signal would be unacceptably slow and have a very high skew. Therefore, multiplexer 205 is typically buffered, for example, as shown in FIGS. 3A and 3B.
FIG. 3A shows a prior art clock driver circuit 320 that includes an inverting clock divider 314. Multiplexer 205 has been replaced by multiplexing circuit 325, which implements the logical equivalent of multiplexer 205 with the input signal from the clock divider inverted by inverter 306.
One implementation of multiplexing circuit 325, designated 325A in FIG. 3A, includes a tristate driver 326, to which the output of inverting clock divider 314 is applied, and passgate 327, to which the bypass clock signal is applied. By controlling the tristate control signal of tristate driver 326 and the passgate control signals of passgate 327, either the divided clock signal or the bypass clock signal is selected. Note, however, that the bypass clock signal is still not buffered in this embodiment, so another buffer (not shown) may be inserted after passgate 327 for heavily-loaded clock signals.
FIG. 3B shows a prior art clock driver circuit 330 that includes a non-inverting clock divider 324. Multiplexer 205 has been replaced by multiplexing circuit 335, which implements the logical equivalent of multiplexer 205 with an output signal buffered through buffer 309.
One implementation of multiplexing circuit 335, designated 335A in FIG. 3B, includes a first tristate driver 336, to which the output of non-inverting clock divider 324 is applied, and a second tristate driver 337, to which the bypass clock signal is applied. By controlling the tristate control signals of tristate drivers 336 and 337, either the divided clock signal or the bypass clock signal is selected. The selected clock signal is then inverted and buffered by inverter 339.
However, the clock driver circuits shown in FIGS. 3A and 3B have implicit additional delays that can be significant. The additional delay D320 added by the clock divider in FIG. 3A is the delay through clock divider 314 plus the delay through tristate driver 326. The additional delay D330 added by the clock divider in FIG. 3B is the delay through the clock divider 324 plus the delay through tristate driver 336 and inverter 339.
Delay through a clock driver circuit is an important parameter for IC designers. Using circuits similar to those shown in FIGS. 3A and 3B, the additional delay due to the presence of a clock divider can be significant, e.g., about 500 picoseconds. Like most timing parameters, this delay is typically specified as a worst-case value, to ensure operation of the device under worst-case conditions. Therefore, even when the clock divider is bypassed, the specifications for the device are based on the worst case scenario, i.e., the delay when the clock divider is included. Therefore, the additional delay on the clock path due to the presence of a clock divider not only delays the clock signal, it also makes the IC device appear to be slower than it really is.
For these and other reasons, it is advantageous to provide a clock divider circuit having a reduced delay.
The invention provides a novel clock divider circuit that adds very little additional delay to the clock driver containing the circuit. Further, according to one embodiment, the clock divider circuit of the invention provides the capability to divide by any even number, rather than being limited to powers of two as are many clock dividers. The delay through the clock divider circuit is the same, regardless of which even number is selected as the divisor.
In one embodiment of the invention, a clock divider circuit includes a state machine that receives the input clock signal and generates set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown, respectively, on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.
An advantage of this circuit is that the delays typical of prior art clock dividers (D-flip-flop delays, multiplexer delays, and so forth) are shifted from the clock path to the path including the set and reset control signals. Therefore, these delays are not on the clock path, i.e., not on the critical path for the clock divider circuit.
Another advantage is that by controlling the functionality of the state machine, any even number (up to the capacity built into the state machine) can be selected as the divisor for the clock divider circuit. Therefore, the clock divider circuit of the invention provides additional flexibility compared to many known clock dividers.
In one embodiment, a phase bit is provided. The phase bit allows the user to either start the clock divider circuit at the first rising edge of the input clock or to delay the clock divider circuit for a predetermined number of clock cycles.
In another embodiment, the clock divider circuit is designed to complete the last high pulse (e.g., to clock in the most recent data value) if the user miscounts the number of clock cycles and mistakenly resets the clock in the middle of the clocking process.
According to another aspect of the invention, a clock driver circuit includes an input buffer, a bypass passgate, and a tristateable clock divider circuit. Rather than using a multiplexer circuit to select between the bypass signal and the output of the clock divider circuit, the clock divider circuit can be tristated. Thus, when the clock divider circuit is tristated and the bypass passgate is on, the bypass signal is passed to the clock driver circuit output. When the clock divider circuit is active (not tristated) and the bypass passgate is off, the divided clock signal is passed to the clock driver circuit output. Thus, the additional delay added by the multiplexer circuit used in conventional clock divider circuits is omitted.